EVENT_CNT_0_OVF=Val_0x0, EVENT_CNT_3_OVF=Val_0x0, EVENT_CNT_2_OVF=Val_0x0, EVENT_CNT_1_OVF=Val_0x0, CYCLE_CNT_OVF=Val_0x0
Performance Monitor Overflow Status Clear Register
| EVENT_CNT_0_OVF | Clear overflow for PMU event counter 0. 0 (Val_0x0): When read, it means the event counter has not overflowed. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter has overflowed. When written, it clears the overflow bit to 0. |
| EVENT_CNT_1_OVF | Clear overflow for PMU event counter 1. 0 (Val_0x0): When read, it means the event counter has not overflowed. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter has overflowed. When written, it clears the overflow bit to 0. |
| EVENT_CNT_2_OVF | Clear overflow for PMU event counter 2. 0 (Val_0x0): When read, it means the event counter has not overflowed. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter has overflowed. When written, it clears the overflow bit to 0. |
| EVENT_CNT_3_OVF | Clear overflow for PMU event counter 3. 0 (Val_0x0): When read, it means the event counter has not overflowed. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter has overflowed. When written, it clears the overflow bit to 0. |
| CYCLE_CNT_OVF | Clear overflow for PMU cycle counter. 0 (Val_0x0): When read, it means the cycle counter has not overflowed. When written, it has no effect. 1 (Val_0x1): When read, it means the cycle counter has overflowed. When written, it clears the overflow bit to 0. |